Engineering
FPGA Development
We design FPGA logic in VHDL and Verilog for embedded, automotive and industrial applications where deterministic timing or parallel processing is needed. The work covers partitioning with the companion processor, RTL design, simulation-based verification, timing closure and hardware bring-up, producing verified RTL with testbenches and documentation for long-term maintenance.
Illustrative workflow
- Partition
- Split functions between FPGA fabric and processor.
- RTL
- Implement the design in VHDL or Verilog.
- Verify
- Simulate against requirements and close timing.
- Bring-up
- Bring the design up on target hardware and debug.
Scope
Architecture and RTL design
Verification and timing closure
Bring-up, migration and maintenance
Starting information
System requirements, target device or candidate devices, interface definitions and any existing RTL.
Applicable framework
Designs are delivered for the selected vendor toolchain with testbenches and timing reports. Safety and security requirements, such as bitstream protection, are scoped per product.
Contact
Discuss your product
Tell us about the product, its current stage and the decision you need to make.
Discuss your product